FPGA prototyping has become a standard SoC verification and validation vehicle. However it is very difficult to navigate around system faults due to the absence of improved methodologies and EDA technology, which are needed for today’s complicated SoC debug process.
The InPA Systems integrated Active DebugTM and Full Visibility technology provides a powerful prototype solution to accelerate time-to-pre-silicon-prototypes. In a normal FPGA prototype environment, there is low visibility into the FPGA and frequent iterations with FPGA P&R. InPA’s technology integrates custom or off-the-shelf FPGA prototype hardware with the RTL simulator environment so the designer can bring up the design with confidence and use the FPGA prototype hardware to accelerate regression simulation. The Embedded Vector Processor Interface (EVPI) is inserted along with the Design Under Verification (DUV) onto the FPGAs and facilitates communication between the simulator and the DUV.
Once the design is successfully mapped into the FPGA prototype the InPA technology allows close control of the debugging process giving engineers expansive triggering capabilities with its Embedded Micro Machines (EMMs) and can capture faulty conditions over multiple FPGAs while giving the engineer full visibility in the debug process.
The InPA Systems integrated Active DebugTM and Full Visibility technology provides a powerful prototype solution to accelerate time-to-pre-silicon-prototypes. In a normal FPGA prototype environment, there is low visibility into the FPGA and frequent iterations with FPGA P&R. InPA’s technology integrates custom or off-the-shelf FPGA prototype hardware with the RTL simulator environment so the designer can bring up the design with confidence and use the FPGA prototype hardware to accelerate regression simulation. The Embedded Vector Processor Interface (EVPI) is inserted along with the Design Under Verification (DUV) onto the FPGAs and facilitates communication between the simulator and the DUV.
Once the design is successfully mapped into the FPGA prototype the InPA technology allows close control of the debugging process giving engineers expansive triggering capabilities with its Embedded Micro Machines (EMMs) and can capture faulty conditions over multiple FPGAs while giving the engineer full visibility in the debug process.